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Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier TUA6024-2 Version 2.0
Specification July 2001
Confidential Revision History: Current Version: Preliminary Datasheet, V 1.1, August 2000 Previous Version:Target Data Sheet Page (in previous Version) all 5-2 Page (in current Version) all 5-2 Subjects (major changes since last revision)
version to 1.1, status to preliminary Bus input/output SDA max changed to 6V, Bus input SCL max changed to 6V, ADC input added new reference for ESD protection Current consumption for LOW/MID band and HIGH band added, tbf's replaced by data Charge Pump output voltage VCP = 1.3 V min Table 5 - 4, Bit Allocation Read/Write in Status Byte A2, A1, A0 added
5-3 5-5
5-3 5-5
5 - 10
5 - 10
Revision History: Current Version: Datasheet, V 2.0, July 2001 Previous Version:Preliminary Datasheet V 1.1, August 2000 Page (in previous Version) all 5-2 5-5 Page (in current Version) all 5- 2 5-5 Subjects (major changes since last revision)
version to 2.0, preliminary deleted definition of thermal properties changed current consumtion changed
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TUA6024-2
Product Info
Product Info
General Description The TUA6024-2 is a 5 V mixer/oscilla- Package tor and synthesizer for TV and VCR tuners. General
s
Features
Suitable for analog tuners and for digital CATV tuners Compatible with TUA6024-S and TUA6024-K in normal mode New features in extended mode Full ESD protection
s
s s
Mixer/Oscillator
s
High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band 4 pin oscillator for HIGH band
PLL
s s s s s
s
PLL with short lock-in time High voltage VCO tuning output Fast I 2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch Lock-in flag Power-down reset 4 programmable reference divider ratios: 24, 64, 80, 128 4 programmable charge pump currents
s s
IF-Amplifier
s s
s s s
balanced SAW preamplifier Low output impedance
s
Application
s
The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top receivers for analog TV and digital cable TV.
Ordering Information
Type TUA6024-2 Ordering Code Q67037--A1161 ( tape and reel) Package P-TSSOP-28-1
Wireless Components
Product Info
Specification, July 2001
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 4 4.1 4.2 5 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 5.5.1 5.5.2 5.5.3 5.5.4
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-19 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA6024-2
Product Description
2.1 General Description
The TUA6024-2 device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners. The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1024 MHz in increments of 31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports. A flag is set when the loop is locked. It can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
s s s s
Suitable for analog tuners and for digital CATV tuners Compatible with TUA6024-S and TUA6024-K in normal mode New features in extended mode Full ESD protection
Mixer/Oscillator
s s s s
High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band 4 pin oscillator for HIGH band
IF-Amplifier
s s
balanced SAW preamplifier Low output impedance
PLL
s s s s s
PLL with short lock-in time High voltage VCO tuning output Fast I2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch
Wireless Components
2-2
Specification, July 2001
TUA6024-2
Product Description
s s s s
Lock-in flag Power-down reset 4 programmable reference divider ratios: 24, 64, 80, 128 4 programmable charge pump currents
2.3 Application
s
The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top receivers for analog TV and digital cable TV.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-3
Specification, July 2001
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TUA6024-2
Functional Description
3.1 Pin Configuration
OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN OSCLOW/MIDIN OSCLOW/MIDOUT OSCLOW/MIDOUT OSCLOW/MIDIN RFGND ADC IFOUT IFOUT VT CP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
HIGHIN HIGHIN LOW/MIDIN VCC MIXOUT MIXOUT PLLGND SDA SCL AS XTAL PHIGH PMID PLOW
TUA6024-2
22 21 20 19 18 17 16 15
TUA6024-2_pin_config
Figure 3-1
Pin Configuration
Wireless Components
3-2
Specification, July 2001
TUA6024-2
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 1 2 3 4 OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN
1 4 2 3
HIGH 1.6 V 2.8 V 2.8 V 1.6 V
0.0 V 0.0 V 0.0 V 0.0 V
5
OSCLOW/ MIDIN
1.6 V
0.0 V
6
OSCLOW/ MIDOUT
6
7
2.3 V
0.0 V
7
OSCLOW/ MIDOUT
5
8
2.3 V
0.0 V
8
OSCLOW/ MIDIN
1.6 V
0.0 V
Wireless Components
3-3
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 9 10 RFGND ADC analog ground 0.0 V VADC HIGH 0.0 V VADC
10
11
IFOUT
2.3 V
2.3 V
11
12
12
IFOUT
2.3 V
2.3 V
13
VT
VT
VT
14
14
CP
13
2.1 V
2.1 V
Wireless Components
3-4
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 15 PLOW
15 16 17
HIGH 5V
5 V or V CE
16
PMID
5 V or V CE
5V
17
PHIGH
5V
V CE
18
XTAL
3.0 V
3.0 V
18
19
AS
VAS
VAS
19
20
SCL
n.a.
n.a.
20
Wireless Components
3-5
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 21 SDA n.a. HIGH n.a.
21
22 23
PLLGND MIXOUT
digital ground
0.0 V 3.8 V
IF A m p.
0.0 V 3.8 V
23
24
24
MIXOUT
3.8 V
3.8 V
O scilla to r
25 26
VCC LOW/MIDIN
supply voltage
5.0 V 1.8 V
5.0 V 0.0 V
26
27
HIGHIN
0.0 V
0.9 V
28
HIGHIN
27
28
0.0 V
0.9 V
Wireless Components
3-6
Specification, July 2001
TUA6024-2
Functional Description
3.3 Block Diagram
LOW/MIDIN
HIGHIN
HIGHIN
MIXOUT
MIXOUT
PLLGND
PHIGH
XTAL
VCC
SDA
SCL
28
27
26
25
VCC LOW or MID
24
23
22
21
20
19
AS
18
17
16
PMID
Charge Pump 13
15
I2C Bus RF Input LOW/MID
PORTS
RF Input HIGH
HIGH
FL
Lock Detector
LOW or MID
Crystal Oscillator
Mixer HIGH
HIGH
Mixer LOW/MID
ADC Reference Divider Prog. Divider
fref
fdiv
LOW or MID
Oscillator HIGH
HIGH
Oscillator LOW/MID
SAW Driver
Phase/ Frequency Comparator
CP, CM, OS
1
2
3
4
5
6
7
8
9
10
11
12
14
OSCHIGHIN
OSCLOW/MIDIN
OSCHIGHIN
OSCHIGHOUT
OSCLOW/MIDOUT
ADC
IFOUT
OSCLOW/MIDIN
RFGND
IFOUT
VT
OSCHIGHOUT
OSCLOW/MIDOUT
CP
PLOW
Block_diag
Figure 3-2
Block Diagram
Wireless Components
3-7
Specification, July 2001
TUA6024-2
Functional Description
3.4 Circuit Description
3.4.1
General
In the normal mode (see Table 5-7 Test modes on page 31) the IC is compatible with TUA6024-S and TUA6024-K. An extended mode makes a reference divider ratio of 24 (see Table 5-8 Reference divider ratio on page 31) and two additional charge pump currents (see Table 5-9 Charge pump current on page 32) available.
3.4.2
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an IF amplifier, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance input and in case of HIGH a low-impedance input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.3
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or 166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4 MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite polarity as charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the positive current source pulses for the duration of the phase difference. In the reverse case the negative current source pulses. If the two signals are in phase, the charge pump output (CP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pull-up resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state if the
Wireless Components
3-8
Specification, July 2001
TUA6024-2
Functional Description
control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. TUNE may be switched off by the control bit OS to allow external adjustments. If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V . By means of the control bits CP, CM, T0 and T1 the pump current can be switched between four values by software. This programmability permits alteration of the control response time of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports PLOW, PMID and PHIGH are general-purpose open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test signals fref (i.e.fXTAL / 64) and f div (divided input signal) to PLOW and PMID respectively. The lock detector resets the lock flag FL if the width of the charge pump current pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fXTAL) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-2 Evaluation Board, low phase noise application on page 20). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock.
3.4.4
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table "Bit Allocation" (see Table 5-4 Bit Allocation Read / Write on page 30) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA
Wireless Components
3-9
Specification, July 2001
TUA6024-2
Functional Description
line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists the lock flag and the power-on flag. Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 31).
While applying the supply voltage, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset at the end of a READ operation.
Wireless Components
3 - 10
Specification, July 2001
4
Applications
Contents of this Chapter 4.1 4.2 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3
TUA6024-2
Applications
4.1 Evaluation board, PAL application
RGen = 75 HIGH
RGen = 75 LOW/ MID VCC
SDA
SCL
AS
PHIGH PMID
PLOW
1:1*)
4n7 68p 68p 47n
100p 220
100p 220
4n7 4 MHz 18p
4n7
4n7
4n7
22p
22p
1n L4
2p2 28 27 26 25 24 23 22 21 20 19 18 17 16 15
TUA6024-2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1 47n 12p 22k
1p2
1p2
1p2
1p2
2p7
2p2
2p2
2p7
100p
L1
L2
L3
120p
ADC 1k 100n
2:10**)
C2 2n2
15p 82p 1k8 BB565 1k8
1p BA892 1n
220 3k3 1k RLoad = 75 2k7 10n BB659C 2k7 IFoutput 100k 33k 560
4n7 + 33 V
TUA6024-2_application-circuit
Figure 4-1
Evaluation Board, PAL application Table 4-1 Coils turns L1 L2 L3 L4 *) **) 1.5 2.5 8.5 14.5 E 2.4 mm 3mm 3.2 mm 4 mm wire E 0.5 mm 0.5 mm 0.5 mm 0.3 mm
Table 4-1 Recommended band limits in MHz RF input min LOW MID HIGH 48.25 147.25 431.25 max 140.25 423.25 855.25 Oscillator min 87.15 193.15 470.15 max 179.15 462.15 894.15
TOKO B4F Type 617DB-1023 TOKO 7KL600 GCS-A1010DX
Wireless Components
4-2
Specification, July 2001
TUA6024-2
Applications
4.2 Evaluation board, low phase noise application
RGen = 75 HIGH
RGen = 75 LOW/ MID VCC
SDA
SCL
AS
PHIGH PMID
PLOW
1:1*)
4n7 68p 68p 47n
100p 220
100p 220
4n7 4 MHz 18p
4n7
4n7
4n7
22p
22p
1n L4
2p2 28 27 26 25 24 23 22 21 20 19 18 17 16 15
TUA6024-2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1 100n 12p 12k
1p2
1p2
1p2
1p2
2p7
2p2
2p2
2p7
100p
L1
L2
L3
120p
ADC 1k 100n
2:10**)
C2 2n2
15p 82p 1k8 BB565 1k8
1p BA892 1n
220 3k3 1k RLoad = 75 2k7 47n BB659C 2k7 IFoutput 4n7 + 33 V 22n 560 100k 33k 560
TUA6024-2_application-circuit
Figure 4-2
Evaluation Board, low phase noise application Table 4-1 Coils turns L1 L2 L3 L4 *) **) 1.5 2.5 8.5 14.5 E 2.4 mm 3mm 3.2 mm 4 mm wire E 0.5 mm 0.5 mm 0.5 mm 0.3 mm
Table 4-1 Recommended band limits in MHz RF input min LOW MID HIGH 48.25 147.25 431.25 max 140.25 423.25 855.25 Oscillator min 87.15 193.15 470.15 max 179.15 462.15 894.15
TOKO B4F Type 617DB-1023 TOKO 7KL600 GCS-A1010DX
Wireless Components
4-3
Specification, July 2001
5
Reference
Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-9 Charge pump current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5-10 Bandswitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5-11 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 5.5.1 5.5.2 5.5.3 5.5.4 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-19 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
TUA6024-2
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20C ...TAmax Parameter 1). Symbol Limit Values min Supply voltage Ambient temperature VCC TA -0.3 -10 max 6 TAmax
2).
Unit
Remarks
V C C C K
Junction temperature Storage temperature Temperature difference junction to case 3). PLL CP
TJ TStg TJC -40
+125 +125 2
VCHGPMP ICHGPMP
-0.3
3 1 VCC
V mA V mA
Crystal oscillator pin XTAL
VXTAL IXTAL -5 -0.3
Bus input/output SDA Bus output current SDA Bus input SCL Chip address switch AS VCO tuning output (loop filter) ADC input Port outputs PLOW, PMID, PHIGH
VSDA ISDA(L) VSCL VAS VT VADC VP IP(L)
6 5
V mA V V V V V mA mA tmax = 0.1 sec. at 5.5 V tmax = 0.1 sec. at 5.5 V open collector
-0.3 -0.3 -0.3 -0.3 -0.3 -1
6 VCC 35 VCC VCC 25 40
Total port output current
IP(L)
Wireless Components
5-2
Specification, July 2001
TUA6024-2
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20C ... + 85C (continued) Parameter 1) Symbol Limit Values min Mixer-Oscillator Mix input LOW/MID Mix inputs HIGH Vi Vi Ii VCO base voltage VCO collector voltage ESD-Protection 4). all pins VESD 2 kV VB VC -5 -0.3 -0.3 3 2 6 3 VCC V V mA V V max Unit Remarks
1). All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. 2).The maximum ambient temperature depends on the mounting conditions of the package. Any application mounting must guarantee not to exceed the maximum junction temperature of 125 C. As reference the temperature difference junction to case is given. 3).Referred to top center of package 4). According to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.
Wireless Components
5-3
Specification, July 2001
TUA6024-2
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range Parameter Symbol Limit Values min Supply voltage Programmable divider factor LOW/MID Mixer input frequency range HIGH Mixer input frequency range LOW/MID Oscillator frequency range HIGH Oscillator frequency range Ambient temperature VCC N fi fi fO fO TAMB +4.5 256 30 400 65 430 -20 max +5.5 32767 500 900 560 950 TAmax
1).
Unit
Test Conditions
L
Item
V
MHz MHz MHz MHz C
1).see 5.1.1 Absolute Maximum Ratings on page 2
Wireless Components
5-4
Specification, July 2001
TUA6024-2
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-3 AC/DC Characteristics with TAMB = 25 C, V CC Symbol min Supply Supply voltage Current consumption VCC ICC 4.5 48 51 5 61 65 5.5 74 79 V mA mA LOW/MID band HIGH band Limit Values typ max Unit Test Conditions L Item
Digital Unit
PLL Crystal oscillator connections XTAL Crystal frequency Crystal resistance Oscillation frequency Input impedance fXTAL RXTAL fXTAL ZXTAL 3.2 10 3,99975 -500 4,000 -700 4.0 4.8 100 4,00025 -900 MHz MHz series resonance series resonance fXTAL = 4 MHz fXTAL = 4 MHz
Charge pump output CP Output current, see Table 5-9 Charge pump current on page 12 ICPDH ICPH ICPDL ICPL Tristate current Output voltage ICPZ VCP 1.3 430 180 90 35 650 250 125 50 1 2.5 860 360 180 70 A A A A nA V VCP = 1.8 V VCP = 1.8 V VCP = 1.8 V VCP = 1.8 V T0 = 1, T1 = 0 PLL locked
Drive output VT (open collector) HIGH output current LOW output voltage I2C-Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A VIH = V CC VIL = 0 V ITH VTL 10 0.4 A V VTH = 33 V, T0 = 1, T1 = 0 ITL = 1.0 mA
Wireless Components
5-5
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 C, V CC (continued) Symbol min Bus output SDA (open collector) HIGH output current LOW output voltage Edge speed SCL,SDA Rise time Fall time Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA Pulse width of spikes which are suppressed Capacitive load for each bus line tsudat thdat Vhys tsp CL 0 0.1 0 200 50 400 s s mV ns pF tsusto tbuf 0.6 1.3 s s tsusta thsta 0.6 0.6 s s fSCL tH tL 0 0.6 1.3 400 kHz s s tr tf 300 300 ns ns IOH VOL 10 0.4 A V VOH = 5.5 V IOL = 3 mA Limit Values typ max Unit Test Conditions L Item
Port outputs PLOW, PMID, PHIGH (open collector) HIGH output current LOW output voltage ADC port input HIGH input current LOW input current IADCH IADCL -10 10 A A IPOH VPOL 1 0.5 A V VPOH = 5 V IPOL = 25 mA
Address selection input AS HIGH input current LOW input current IASH IASL -50 50 A A VASH = 5 V VASL = 0 V
Wireless Components
5-6
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 C, V CC (continued) Symbol min Limit Values typ max Unit Test Conditions L Item
Analog Unit
LOW/MID Band Section (including IF amplifier) Voltage gain GV 20 23 26 dB fRF = 43.25 to 463.25 MHz, fIF = 33.4 to 58.75 MHz fRF = 43.25 to 463.25 MHz fRFw = 48.25 MHz fRFw = 399.25 MHz
Mixer noise figure Output voltage causing 0.8% of crossmodulation in channel, see 5.4.6 on page 17 Input IP2
NF Vi Vi
9 118 117
11
dB dBV dBV
IIP2
137
dBV
fRF1 = 48.25 MHz fRF2 = 98.50 MHz, PRF1 = P RF2 fRF1 = 415.25 MHz fRF2 = 832.50 MHz, PRF1 = P RF2 fRF1 = 48.25 MHz fRF2 = 49.25 MHz PRF1 = P RF2 fRF1 = 252.25 MHz fRF2 = 253.25 MHz, PRF1 = P RF2 fRF = 48.25 MHz fRF = 252.25 MHz parallel equivalent circuit, fRF = 100 MHz parallel equivalent circuit, fRF = 100 MHz VCC = 5 V10% T = 25 C t = 5 s up to 15 min after switching on
IIP2
137
dBV
Input IP3
IIP3
119
dBV
IIP3
119
dBV
Output voltage causing 1 dB compression Mixer input impedance
Vo Vo Ri 0.5
121 121 1 1.5
dBV dBV k
Ci
2
3
pF
Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked
fOsc(V) fOsc(T) fOsc(t)
400 500 100
kHz kHz kHz
Wireless Components
5-7
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 C, V CC (continued) Symbol min Oscillator pulling, PLL unlocked Vi 100 100 Vi N + 5 pulling, PLL unlocked N+5 -50 dBc Limit Values typ 108 108 max dBV dBV f = 10 kHz fRF = 48.25 MHz f = 10 kHz fRF = 399.25 MHz fRF = 48.25 MHz, fRF1 = 83.25 MHz, PRF=P RF1 = 80dBV fRF = 399.25 MHz, fRF1 = 439.25 MHz, PRF=P RF1 = 80dBV fm = 1kHz fm = 10kHz VIF = 80 dBV Unit Test Conditions L Item
N+5
-50
dBc
Oscillator phase noise 1). IF suppression
OSC
-58 -88
-60 -90 20
dBc/Hz dBc/Hz dB
aIF
15
HIGH Band Section (including IF amplifier) Voltage gain GV 31 34 37 dB fRF = 367.25 MHz to 863.25 MHz, fIF = 33.4MHz to 58.75 MHz fRF = 367.25 to 615.25 MHz fRF = 623.25 to 863.25 MHz fRFw = 503.25 MHz fRFw = 799.25 MHz
Mixer noise figure
NF
6 7
9 10
dB dB dBV dBV
Output voltage causing 0.8% of crossmodulation in channel, see 5.4.7 on page 18 Input IP2
Vi Vi
116 117
IIP2
139
dBV
fRF1 = 423.25 MHz fRF2 = 848.50 MHz, PRF1 = PRF2 fRF1 = 503.25 MHz fRF2 = 504.25 MHz PRF1 = PRF2 fRF1 = 799.25 MHz fRF2 = 800.25 MHz PRF1 = PRF2 fRF = 503.25 MHz fRF = 799.25 MHz
Input IP3
IIP3
108
dBV
IIP3
108
dBV
Output voltage causing 1 dB compression
Vo Vo
121 121
dBV dBV
Wireless Components
5-8
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 C, V CC (continued) Symbol min Mixer input impedance Ri Li Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator pulling, PLL unlocked fOsc(V) fOsc(T) fOsc(t) Vi 100 100 N + 5 pulling, PLL unlocked Vi -50 108 108 14 6 Limit Values typ 20 10 max 26 14 400 800 100 nH kHz kHz kHz dBV dBV dBc serial equivalent circuit, fRF = 600 MHz serial equivalent circuit, fRF = 600 MHz VCC = 5 V10% T = 25 C t = 5 s up to 15 min after switching on f = 10 kHz fRF = 375.25 MHz f = 10 kHz fRF = 847.25 MHz fRF = 471.25 MHz, fRF1 = 511.25 MHz, PRF =PRF1 = 80dBV fRF = 847.25 MHz, fRF1 = 887.25 MHz, PRF=P RF1 = 80 dBV fm = 1kHz fm = 10kHz Vi = 80 dBV Unit Test Conditions L Item
Vi
-50
dBc
Oscillator phase noise
1.)
OSC
-58 -88
-60 -90 20
dBc/Hz dBc/Hz dB
IF suppression SAW preamplifier IF output impedance
aIF
15
RIF LIF
125 10
nH
serial equivalent circuit, fIF = 38.9 MHz
Rejection at the IF outputs Divider interference level
2).
Vo a 66
30
dBV dBc fRF = 76.25 MHz PRF = 80 dBV
Channel S02 beat rejection 3).
s This value is only guaranteed in lab.
1). Measured in the evaluation board (see Chapter 4), worst case in band. 2). This is the level of divider interferences close to the IF frequency. For example channel S3: fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Divider interference is measured in the evaluation board (see Chapter 4). 3). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz. The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in the evaluation board (see Chapter 4).
Wireless Components
5-9
Specification, July 2001
TUA6024-2
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write Byte Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte Bandswitch Byte 1). Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 x 0 x MA1 A2 MA0 A1 1 A0 A A 1 0 N7 1 x 1 N14 N6 CP x 0 N13 N5 T1 x 0 N12 N4 T0 x 0 N11 N3 CM P3 MA1 N10 N2 RSA P2 MA0 N9 N1 RSB P1 0 N8 N0 OS P0 A A A A A MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB Ack Remark
1). see Table 5-10 Bandswitching on page 12
Table 5-5 Description of symbols Symbol MA0, MA1 N14 to N0 CP T1, T0 CM RSA, RSB OS Description Address selection bits (see Table 5-6 Address selection on page 11) programmable divider bits: N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0 charge pump current: bit = 0: charge pump current = 50 A bit = 1: charge pump current = 250A
test bits (see Table 5-7 Test modes on page 11) charge pump mode bit (see Table 5-9 Charge pump current on page 12) reference divider bits (see Table 5-8 Reference divider ratio on page 11) tuning amplifier control bit: bit = 0: enable VT bit = 1: disable VT bit = 0: NPN open-collector output is inactive bit = 1: NPN open-collector output is active
PLOW, PMID, PHIGH, see 5-10 on page 12 A0, A1, A2 FL POR x
NPN ports control bits:
ADC bits (see Table 5-11 A/D converter levels on page 13) PLL lock flag bit = 1: loop is locked
Power-on reset flag flag is set at power-on and reset at the end of READ operation don`t care
Wireless Components
5 - 10
Specification, July 2001
TUA6024-2
Reference
Table 5-6 Address selection Voltage at AS (0...0.1) * V CC (0.2...0.3) * VCC or open circuit (0.4...0.6) * V CC (0.9...1) * V CC MA1 0 0 1 1 MA0 0 1 0 1
Table 5-7 Test modes Test mode Normal operation Charge pump output, CP is in high-impedance state PMID = fdiv output, PLOW = fref output Extended operation extended normal
1).
Mode
T1 0 0 1 1
T0 0 1 0 1
1). In this mode the IC is compatible with TUA6024-S and TUA6024-K
Table 5-8 Reference divider ratio Reference divider ratio 80 Mode 1). T1 0 0 1 0 128 normal 0 1 0 64 0 1 80 128 24 64 1). see Table 5-7 Test modes on page 11 2). With a 4 MHz quartz. extended 1 1
T0
0 1 0 0 1 0 0 1 0
RSA x
RSB 0
fref 2). 50 kHz
0
1
31.25 kHz
1
1
62.5 kHz
0 0 1 1
0 1 0 1
50 kHz 31.25 kHz 166.7 kHz 62.5 kHz
Wireless Components
5 - 11
Specification, July 2001
TUA6024-2
Reference
Table 5-9 Charge pump current Charge pump current 50 A 250 A 50 A 125 A 250 A 600 A 1). see Table 5-7 Test modes on page 11 extended normal Mode 1). CP 0 1 0 0 1 1 1 1 0 0 T1 T0 CM x x 0 1 0 1
Table 5-10 Bandswitching Bit Designation Active Port PHIGH 1). PLOW PMID not used PHIGH PLOW PMID not used PHIGH PLOW PMID not used PHIGH PLOW PMID not used 1). Default after power-on 17 15 16 17 15 16 17 15 16 Pin 17 15 16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P3 P2 P1 P0
Wireless Components
5 - 12
Specification, July 2001
TUA6024-2
Reference
Table 5-11 A/D converter levels Voltage at ADC (0...0.15)*V CC (0.15...0.3)*V CC (0.3...0.45)*V CC (0.45...0.6)*V CC (0.6...1)*V CC A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0
Wireless Components
5 - 13
Specification, July 2001
Wireless Components
Start Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte Ack.
Stop
Addressing
1
1
0
0
0
MA1 MA0 R/W
5.3 I2C Bus Timing Diagram
5 - 14
Note: SDA:
SCL:
Telegram examples:
Abbreviations:
Start-ADB-DB1-DB2-CB-BB-Stop ADB= address byte
Start= start condition
Start-ADB-CB-BB-DB1-DB2-Stop
Start-ADB-DB1-DB2-Stop
DB1= prog. divider byte 1 DB2= prog. divider byte 2 CB= Control byte BB= Bandswitch byte Reference Stop= stop condition
Start-ADB-CB-BB-Stop
Specification, July 2001
TUA6024-2
TUA6024-2
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID
50 Vmeas RMS Voltmeter
LOW/ MIDIN
IFOUT
Transformer N1 V0 C V'meas N2 50 spectrum analyser
V
50
Vi
Device under Test
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
s s s s
Zi >> 50 => V i = 2 x Vmeas = 80 dBV Vi = Vmeas + 6dB = 80 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi)
5.4.2
Gain (GV) test Set-up in HIGH
HIGHIN IFOUT 50 Vmeas RMS Voltmeter
Transformer N1 V0 C V'meas N2 50 spectrum analyser
V
50
Vi
Balun 1:1
Device under Test
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
s s s
Vi = Vmeas = 70 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
Wireless Components
5 - 15
Specification, July 2001
TUA6024-2
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID
22p In
1n Out 7 turns wire 0.5 mm coil 5.5 mm In
15p
1n Out
22p
50 semi rigid cable 300 mm long 96 pF/m 33dB/100m
22p
NFM
For fRF = 50 MHz
s s
For fRF = 150 MHz
s s
loss = 0 dB image suppression = 16 dB
loss = 1.3 dB image suppression = 13 dB
5.4.4
Noise Figure Test Set-up in LOW/MID
Noise Source
IN
OUT
LOW/ MIDIN
IFOUT
Transformer N1 C N2
Matching Circuit
Device under Test
IFOUT
Noise Figure Meter
N1 : N2 = 10 : 2 turns NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 16
Specification, July 2001
TUA6024-2
Reference
5.4.5
Noise Figure Test Set-up in HIGH
Noise Source
HIGHIN IFOUT
Transformer N1 C N2
Balun 1:1
Device under Test
HIGHIN IFOUT
Noise Figure Meter
N1 : N2 = 10 : 2 turns loss of balun = 1 dB NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6
Cross modulation Test Set-up in LOW/MID band
Vmeas unwanted signal source AM = 80 % A 50 C RMS Voltmeter
V
50
LOW/ MIDIN
IFOUT
Transformer N1 V0 C N2
18 dB attenuator 38.9 MHz
Hybrid
50 B wanted signal source D 50
Vi
Device under Test
IFOUT
V
V'meas RMS Votmeter
50 modulation analyser
N1 : N2 = 10 : 2 turns
XVHF2
s s s s
Zi >> 50 => Vi = 2 x Vmeas V'meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBV unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
Wireless Components
5 - 17
Specification, July 2001
TUA6024-2
Reference
5.4.7
Cross modulation Test Set-up in HIGH band
Vmeas unwanted signal source AM = 80 % A 50 C RMS Voltmeter
V
50
HIGHIN IFOUT
Transformer N1 V0 C N2
18 dB attenuator 38.9 MHz
Hybrid
50 B wanted signal source D 50
Vi
Balun 1:1
Device under Test
HIGHIN IFOUT
V
V'meas RMS Votmeter
50 modulation analyser
N1 : N2 = 10 : 2 turns
XUHF2
s s s
V'meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBV unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
5.4.8
Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0 5k 5k
Device under Test
PMID
fref
Counter
fQ = fref * R R: reference divider ratio
18p 4 MHz
PLOW fdiv
Counter
fVCO = fdiv * N N: divider ratio
freq_meas_cof
Wireless Components
5 - 18
Specification, July 2001
TUA6024-2
Reference
5.5 Electrical Diagrams
5.5.1
Input admittance (S11) of the LOW/MID band mixer input
Y0 = 20mS (single ended)
1
0.9
0.8
1.5
0.7
0.6
0.5
0.4
2 3
1.5 1 0.9 0.8 0.7 0.6 0.5 0.4
0.3
0.3
0.2
0.1
20
10
5
4
3
2
20
48.25 MHz
0.1
10
407.25 MHz
0.2 5
4
3
0.4
1.5
5.5.2
Input impedance (S11) of the HIGH band mixer input
Z0 = 50 (balanced)
0.7
0.8
0.9
1
1
0.9
0.8
0.6
1.5
0.7
0.6
0.5
2
0.5
2
3
0.3
4
5
855.25 MHz
10 0.1
415.25 MHz
20
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9 1
1.5
Rdiff
10
0
20
20
2
3
4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Wireless Components
5 - 19
1
1.5
2
Specification, July 2001
5
0.2
10
0.1
5
0
4
0.3
3
0.4
4
0.2 0.2 5
10
20
0.1
TUA6024-2
Reference
5.5.3
Output admittance (S22) of the Mixer output
Y0 = 20mS (balanced)
1
0.9
0.8
1.5
0.7
0.6
0.5
0.4
2 3
1.5 1 0.9 0.8 0.7 0.6 0.5 0.4
0.3
0.3
0.2
20
4
3
0.4
1.5
5.5.4
Output impedance (S22) of the IF output
Z0 = 50 (single/ double ended)
0.7
0.8
0.9
1
1
0.9
0.8
0.6
1.5
0.7
0.6
0.5
2
0.5
2
3
0.3
4
5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9 1
1.5
10
0
Rse
0.1
Rdiff
20
20
10
2
3
4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Wireless Components
5 - 20
1
1.5
2
Specification, July 2001
5
0.2
5
0.2
5
0.1
10
10
20
0
Rdiff 38.9 MHz
4
0.3
0.1
20
10
5
4
3
2
3
0.4
4
0.2 0.2 5
0.1 10
20
0.1

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